Technical Field
The present disclosure relates to a vertical power component capable of withstanding a high voltage (greater than 500 V) and more specifically to the peripheral structure of such a component.
Discussion of the Related Art
FIGS. 1, 2, 3, and 4 are cross-section views showing various ways of forming the periphery of such a high-voltage vertical power component to enable it to withstand high voltages.
These drawings show a triac comprising a lightly-doped N-type silicon substrate 1 (N−), currently with a doping ranging from 1014 to 1015 atoms/cm3, having its upper and lower surfaces comprising P-type doped layers or regions 3 and 5. Upper layer 3 contains a heavily-doped N-type region 4 and lower layer 5 contains a heavily-doped N-type region 6 in an area substantially complementary to that taken up by region 4. An electrode A1 coats the lower surface of the component and is in contact with regions 5 and 6. An electrode A2 coats the upper surface of the component and is in contact with region 4 and a portion of region 3. In region 3 is also formed a heavily-doped N-type region 8 of small extension, and a gate electrode G covers region 8 and a portion of region 3. Thus, whatever the biasing between electrodes A1 and A2, if a gate control is provided, the component turns on. The conduction is performed from electrode A1 to electrode A2 through a vertical thyristor comprising regions 5, 1, 3, and 4, or from electrode A2 to electrode A1 through a vertical thyristor comprising regions 3, 1, 5, and 6. The thickness and the doping level of substrate 1 are calculated so that the triac, in the off state, can withstand high voltages, for example, voltages ranging between 600 and 800 volts. It should then be avoided that breakdowns occur at the component edges.
FIG. 1 shows a so-called double-mesa peripheral structure for avoiding such breakdowns. A ring-shaped lateral trench deeper than P regions 3 and 5 is formed at the periphery of each of the two surfaces of the substrate. These trenches are filled with a passivation glass 9. In practice, trenches are initially formed on a silicon trench between two components before dicing of the chip into individual components. If a breakdown occurs, it occurs in areas 11 where the PN− junctions cut insulating trenches 9.
A disadvantage of double-mesa structures is that, given that the passivation glass never has the same thermal expansion coefficient as silicon, the interface between glass and silicon ages poorly and, in case of an incidental breakdown, if the voltage across the component exceeds the authorized limit, the component is no longer operative.
Another disadvantage of double-mesa is due to the fact that the lateral surfaces of substrate 1 are not insulated. Thus, when the component electrodes are welded to contact areas of another electronic device or of a package, it should be provided that lateral wickings do not electrically connect one of the electrodes to substrate 1, which would short-circuit the corresponding PN− junction.
FIG. 2 shows another conventional peripheral structure of the power component. A groove filled with a passivation glass is present on the upper surface side. The component is surrounded with a heavily-doped P-type diffused wall 12 formed from the upper and lower surfaces and the groove extends between wall 12 and P-type layer 3, substantially as shown. Thus, all voltage hold areas are gathered on the upper surface side of the component. Breakdowns are likely to occur at the periphery of the junction between wall 12 and substrate 1, on the groove side, in the area designated with reference numeral 14, when lower electrode A1 is negative with respect to upper electrode A2 (so-called reverse breakdown); and breakdowns are likely to occur at the periphery of the junction between substrate 1 and layer 3, on the groove side, in the area designated with reference numeral 16, when lower electrode A1 is positive with respect to upper electrode A2 (so-called forward breakdown).
This structure provides good results, and simplifies the forming of lower electrode A1 and the steps of welding to an external device. In particular, the presence of wall 12 thus prevents any risk of short-circuit due to possible lateral wickings.
However, a disadvantage is that distance e2 between the component edge and the glassivation limit (beginning of electrode A2 or G, respectively) is greater than distance e1 between the component edge and the glassivation limit in the former case. As an example, in the best conditions, that is, when the angle according to which the trenches filled with glass cut the junctions between the substrate and layers 3 and 5 is properly chosen, and when the amount of glass is optimized, in order to obtain a breakdown voltage greater than 800 volts, a distance e1 on the order of 300 μm should be provided in the case of FIG. 1, and a distance e2 on the order of 350 μm should be provided in the case of FIG. 2. This decreases, by this distance, the surface area available for the electrodes of the power component of FIG. 2; otherwise, for given values of the electrode surface areas, this increases the surface area of the component, and thus its cost.
Further, as in the previous case, the interface between the silicon and the passivation glass remains a problem.
Further, the presence of grooves only extending on the front surface side of the semiconductor substrate may raise mechanical stress issues.
Further, region 3 being relatively close to diffused wall 12, there is a risk of breakdown of the component by punchthrough of the bipolar transistors formed by P-type region 3, N-type substrate 1, and P-type wall 12, which limits the voltage behavior of the component.
FIG. 3 shows a passivation structure in so-called “planar” technology. As in the case of FIG. 2, the structure is surrounded with a heavily-doped P-type ring-shaped wall at its periphery. To withstand the voltage, a distance is provided between the limit of P-type layer 3 and peripheral wall 20. A breakdown, if any, would occur in regions 23 of curvature of P well 3 or in region 24 of junction between P layer 5 and substrate 1.
An advantage of this structure is that a breakdown is not necessarily destructive for the component. However, this structure has the disadvantage of requiring a channel stop ring 22 at the periphery of the upper surface in the region of N substrate 1 between the limit of P region 3 and the limit of insulating wall 20. This entails the disadvantage of requiring a relatively large guard distance e3 between the component edge and the limit of electrode A2, for example, on the order of 370 μm to withstand a voltage greater than 800 volts.
Further, the method for forming this structure requires a larger number of masks than for previous structures.
FIG. 4 shows another peripheral structure for avoiding breakdowns, which is described in patent application US 2011/0210372. At the component periphery, on the lower surface side, is a heavily-doped P-type diffused wall region 30 crossing P-type layer 5 and penetrating down to a depth into substrate 1 of substantially half the substrate thickness. On the upper surface side, at the component periphery, a deep straight groove 32 joins diffused region 30. Groove 32 is insulated at its periphery by an oxide layer 33 and is filled with undoped silicon 34 in its central portion. To withstand a high voltage, a distance e4 is provided between the limit of P-type layer 3 and the groove 32. In such a structure, forward breakdowns may occur in bending region 36 of P-type layer 3 and reverse breakdowns may occur in region 38 at any point along the lower junction formed by layer 5 and substrate 1. In order to control the extension of the space charge area (especially for the reliability of the forward junction) and avoid any surface inversion phenomenon, a more heavily-doped N area 40 need to be provided in the vicinity of the end of the groove on the upper surface side.
A disadvantage of the structure of FIG. 4 is that, as in the case of FIG. 3, the P-type region 3 is localized in the central portion of the component. Thus, forming the component requires a larger number of masks than for the structures of FIGS. 1 and 2.